1. Field of the Invention
The present invention relates to a voltage-controlled delay line. More specifically, the present invention discloses a voltage-controlled delay line with an improved interconnection among delay cells for reducing timing errors and jitters.
2. Description of the Prior Art
Processing, exchanging, and distributing digital information exists in a broad spectrum of fields. For example, digital devices such as mobile phones, personal digital assistants (PDAs), information applicants (IAS) that are connected to a computer network, and personal computers are utilized to conveniently handle digital information. When the digital device processes, exchanges, and distributes digital information, the digital device requires triggers generated from a clock signal to process digital data that are sequentially transmitted. For instance, a central processing unit (CPU) of a personal computer coordinates data transmitted among digital circuits and data processed among the digital circuits with the help of triggers generated from a clock signal. In addition, with regard to a mobile phone, a clock signal is necessary to let the mobile phone correctly transmit and receive wireless signals. Suppose that the mobile phone functions as a receiver to receive incoming digital signals. In the beginning, the mobile phone has to establish a local clock signal synchronized with a timing associated with the incoming digital signals outputted from a base station. Therefore, the mobile phone successfully transmits wireless signals to the base station and correctly receives wireless signals outputted from the base station according to the local clock signal synchronized with clock signal used by the base station.
During a digital information processing procedure triggered by clock signals, a well-known technique for generating a synchronous clock signal based on a reference clock signal is widely adopted. In digital circuits, a frequency associated with one of two synchronous clock signals is multiplied or divided to further obtain two synchronous clock signals with different frequencies for conveniently handling digital data. In addition, it is possible to generate a synchronous clock signal with a greater driving capacity according to a reference clock signal. With regard to a digital mobile communication system, when a mobile phone, which functions as a receiver, needs to establish a local clock signal according to timing of received signals, the received signals have weak amplitudes so that the driving capacity of the received signals is poor. Therefore, a synchronous clock having a greater driving capacity and corresponding to timing of received signals is necessary to drive the mobile phone to work properly.
A circuit, which is capable of generating a synchronous clock signal according to a reference clock signal, is called a phase lock loop (PLL). One embodiment of the prior art PLL is a so-called delay lock loop (DLL). Please refer to FIG. 1, which is block diagram of a prior art DLL 10. The DLL 10 has a clock generator 11, a voltage-controlled delay line 12, a phase detector 14, a charge pump 16, and two differential-to-single-ended converters 18a, 18b. The clock generator 11 simultaneously outputs a first reference clock signal CLK_REF+ and a second reference clock signal CLK_REFxe2x88x92, where a phase difference between the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92 is equal to 180 degrees. That is, the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92 are out of phase. The voltage-controlled delay line 12, therefore, respectively delays the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92 to generate a first delay clock signal CLK_DL+ and a second delay clock signal CLK_DLxe2x88x92. The differential-to-signal-ended converter 18a outputs a first comparison signal CLK1 based on a magnitude difference between the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92. A period of the first comparison signal CLK1 is identical to a period of the first reference clock signal CLK_REF+, and the period of the first comparison signal CLK1 is identical to a period of the second reference clock signal CLK_REFxe2x88x92 as well. Similarly, the differential-to-single-ended converter 18b outputs a second comparison signal CLK2 based on a magnitude difference between the first delay clock signal CLK_DL+ and the second delay clock signal CLK_DLxe2x88x92.
A period of the second comparison signal CLK2 is theoretically identical to a period of the first delay clock signal CLK_DL+, and the period of the second comparison signal CLK2 is identical to a period of the second delay clock signal CLK_DLxe2x88x92 as well. Then, the phase detector 14 judges if the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ are in phase according to phases of the first comparison signal CLK1 and the second comparison signal CLK2. In addition, the phase detector 14 also judges if the second delay clock signal CLK_DLxe2x88x92 and the second reference clock signal CLK_REFxe2x88x92 are in phase according to phases of the first comparison signal CLK1 and the second comparison signal CLK2. When either rising edges or falling edges of the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ differ by an integral multiple of the period of first reference clock signal CLK_REF+, the first delay clock signal CLK_DL+ and the first reference clock signal CLK_REF+ are in phase. Similarly, when either rising edges or falling edges of the second delay clock signal CLK_DLxe2x88x92 and the second reference clock signal CLK_REFxe2x88x92 differ by an integral multiple of the period of second reference clock signal CLK_REFxe2x88x92, the second delay clock signal CLK_DLxe2x88x92 and the second reference clock signal CLK_REFxe2x88x92 are in phase.
After the phase detector 14 compares phases of the first reference clock signal CLK1 and the second reference clock signal CLK2, the phase detector 14 outputs control signals UP, DOWN to the charge pump 16 according to the reference clock signal CLK1 leading the second reference clock signal CLK2 or the reference clock signal CLK1 lagging the second reference clock signal CLK2. After the charge pump 16 receives the control signal DOWN, the charge pump 16 raises voltage level of a control voltage Vpump. With regard to voltage-controlled delay line 12, the increased control voltage Vpump drives the voltage-controlled delay line 12 to delay the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92 through a longer delay time. On the other hand, after the charge pump 16 receives the control signal UP, the charge pump 16 lowers voltage level of the control voltage Vpump. With regard to voltage-controlled delay line 12, the decreased control voltage Vpump drives the voltage-controlled delay line 12 to delay the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92 through a shorter delay time.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a first timing diagram illustrating a phase lock process, and FIG. 3 is a second timing diagram illustrating the phase lock process. Within FIG. 2 and FIG. 3, the waveforms from top to bottom respectively represent the first comparison signal CLK1, the second comparison signal CLK2, the control signal UP, the control signal DOWN, and time. For example, the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92, which correspond to the first comparison clock CLK1, are inputted into the voltage-controlled delay line 12 at time t1. The voltage-controlled delay line 12 outputs the first delay clock signal CLK_DL+ and the second delay clock CLK_DLxe2x88x92, which correspond to the second comparison signal CLK2, after a delay time (t2xe2x88x92t1).
As shown in FIG. 2, the rising edge of the second comparison clock CLK2 at time t2 leads the rising edge of the first comparison signal CLK1 at time t3. That is, the phase of the second comparison signal CLK2 leads the phase of the first comparison signal CLK1. In other words, the delay time (t2xe2x88x92t1) introduced by the voltage-controlled delay line 12 is less than the period (t3xe2x88x92t1) corresponding to the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92. Therefore, the currently adopted delay time should be increased. Therefore, the phase detector 14 outputs the control signal DOWN at time t2 to the charge pump 16 for raising the control voltage Vpump.
The first comparison signal CLK1 forms a rising edge at time t3. At the same time, the control signal UP is issued by the phase detector 14 during an interval Î. While the phase detector 14 resets the control signal UP, the control signal DOWN is reset as well. Therefore, the control signal UP and the control signal DOWN are both reset at time t3+Î. As shown in FIG. 2, the delay time is now adjusted to be (t4xe2x88x92t3). Because the rising edge of the second comparison signal CLK2 at time t4 still leads the rising edge of the first comparison signal CLK1 at time t5, the phase detector 14 outputs the control signal DOWN at time t4 to the charge pump 16.
When the first comparison signal CLK1 generates the rising edge at time t5, the phase detector 14 outputs the control signal UP during the interval Î. Then, the control signal UP and the control signal DOWN are both reset at time t5+Î. The first comparison signal CLK1 and the second comparison signal CLK2 are in phase at time t6. That is, the first comparison signal CLK1 and the second comparison signal CLK2 form rising edges simultaneously at time t6. Therefore, the phase detector 14 outputs the control signals UP, DOWN to the charge pump 16 during the same interval Î. In other words, the control signals UP, DOWN are both reset at time t6+Î.
Because the both control signals UP, DOWN have the same power to affect the control voltage Vpump, the charge pump 16 therefore holds currently adopted control voltage Vpump without being altered to drive the voltage-controlled delay line 12 for locking the first and second reference clock signals CLK_REF+, CLK_REFxe2x88x92 and the in phase first and second delay clock signals CLK_DL+, CLK_DLxe2x88x92 corresponding to the first and second reference clock signals CLK_REF+, CLK_REFxe2x88x92.
Please refer to FIG. 3, the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92, which correspond to the first comparison clock CLK1, are inputted into the voltage-controlled delay line 12 at time t1. The voltage-controlled delay line 12 outputs the first delay clock signal CLK_DL+ and the second delay clock CLK_DLxe2x88x92, which correspond to the second comparison signal CLK2, after a delay time (t2xe2x88x92t1). As shown in FIG. 3, the rising edge of the second comparison clock CLK2 at time t3 lags the rising edge of the first comparison signal. CLK1 at time t2. That is, phase of the second comparison signal CLK2 lags phase of the first comparison signal CLK1. In other words, the delay time (t3xe2x88x92t1) introduced by the voltage-controlled delay line 12 is greater than the period (t2xe2x88x92t1) corresponding to the first reference clock signal CLK_REF+ and the second reference clock signal CLK_REFxe2x88x92. Therefore, the currently adopted delay time should be cut down. Therefore, the phase detector 14 outputs the control signal UP at time t2 to the charge pump 16 for decreasing the control voltage Vpump.
The second comparison signal CLK1 forms a rising edge at time t3. At the same time, the control signal DOWN is issued by the phase detector 14 during an interval Î. While the phase detector 14 resets the control signal DOWN, the control signal UP is reset as well. Therefore, the control signal UP and the control signal DOWN are both simultaneously reset at time t3+Î. As shown in FIG. 3, the delay time is now adjusted to be (t5xe2x88x92t2). Because the rising edge of the second comparison signal CLK2 at time t5 still lags the rising edge of the first comparison signal CLK1 at time t4, the phase detector 14 outputs the control signal UP at time t4 to the charge pump 16. When the second comparison signal CLK2 generates the rising edge at time t5, the detector 14 outputs the control signal DOWN during the interval Î. Then, the control signal UP and the control signal DOWN are both reset at time t5+Î.
The first comparison signal CLK1 and the second comparison signal CLK2 are in phase at time t6. That is, the first comparison signal CLK1 and the second comparison signal CLK2 form rising edges simultaneously at time t6. Therefore, the phase detector 14 outputs the control signals UP, DOWN to the charge pump 16 during the same interval Î. In other words, the control signals UP, DOWN are both reset at time t6+Î.
Because the both control signals UP, DOWN have the same power to affect the control voltage Vpump, the charge pump 16, therefore, holds currently adopted control voltage Vpump without being altered to drive the voltage-controlled delay line 12 for locking the first and second reference clock signals CLK_REF+, CLK_REFxe2x88x92 and the in phase first and second delay clock signals CLK_DL+, CLK_DLxe2x88x92 corresponding to the first and second reference clock signals CLK_REF+, CLK_REFxe2x88x92.
Please refer to FIG. 4 and FIG. 5. FIG. 4 is a diagram of the voltage-controlled delay line 12 shown in FIG. 1, and FIG. 5 is a circuit diagram of a delay cell 20 shown in FIG. 4. The voltage-controlled delay line 12 has a plurality of delay cells 20 that are cascaded in series. An output port out+ of a delay cell 20 is electrically connected to an input port in+ of a following delay cell. Similarly, an output port outxe2x88x92 of a delay cell 20 is electrically connected to an input port inxe2x88x92 of a following delay cell. As shown in FIG. 5, the delay cell 20 corresponds to a symmetrical circuit structure, and has a first circuit 22, a second circuit 24, and a current source 26. A voltage Vb is used to control current value provided by the current source 26, and the control voltage Vpump outputted from the charge pump 16 is used to control current values corresponding to the first circuit 22 and the second circuit 24. However, with development of the semiconductor process, the size of chips have become smaller. Therefore, the circuits formed on the same chip are much closer together than before. With regard to the deep sub-micro process, one circuit component might easily affect another circuit component.
For the first circuit 22 and the second circuit 24, operational characteristics of both circuits are mismatched owing to the advanced semiconductor process. That is, when the same control voltage Vpump is inputted to the delay cell 20, the first circuit 22 and the second circuit 24 generate different voltage variations so that currents passing through the first circuit 22 and the second circuit 24 differ. Not only is the delay time associated with the input port in+ and the output port out+ different from the delay time associated with the input port inxe2x88x92 and the output port outxe2x88x92, but the phase difference between the input port in+ and the output port out+ and the phase difference between the input port inxe2x88x92 and the output port outxe2x88x92 both deviate from a predetermined value. For instance, if the voltage-controlled delay line 12 has ten delay cells 20, and the input port and the corresponding output port of each delay cell 20 corresponds to a delay time Td. The voltage-controlled delay line 12 has a delay cell 20 with mismatched first and second circuits 22, 24. Therefore, with regard to the first circuit 22, the corresponding delay time becomes Td+dT instead. On the other hand, the delay time of the second circuit 24 then becomes Tdxe2x88x92dT owing to the above-mentioned symmetrical circuit structure.
It is shown in FIG. 4 that the voltage-controlled delay line 12 delays the first reference clock signal CLK_REF+ by a total delay time 10*Td+dT for outputting the first delay clock signal CLK_DL+. However, the voltage-controlled delay line 12 delays the second reference clock signal CLK_REFxe2x88x92 by a total delay time 10*Tdxe2x88x92dT for outputting the second delay clock signal CLK_DLxe2x88x92. It is obvious that each delay cell having mismatched first and second circuits 22, 24 corresponds to a specific degree of influence upon the associated delay time. In the end, problems with respect to timing errors between the first and second reference clock signals CLK_REF+, CLK_REFxe2x88x92 and the first and second delay clock signals CLK_DL+, CLK_DLxe2x88x92 are introduced.
At the same time, the timing errors certainly cause the periods corresponding to the delay clock signals CLK_DL+, CLK_DLxe2x88x92 to change continuously. Therefore, the jitters corresponding to the delay clock signals CLK_DL+, CLK_DLxe2x88x92 are great. If the component size is increased to prevent the above-mentioned mismatch problem when utilizing the deep sub-micro process to manufacture the DLL 10, the chip size increases and the related parasite capacitance increases owing to an enlarged trace width. However, if an additional calibration circuit is utilized to solve the above-mentioned mismatch problem without increasing component size, the hardware complexity will increase to raise an overall product cost.
It is therefore a primary objective of this invention to provide a voltage-controlled delay line capable of reducing timing errors and jitters.
Briefly summarized, the preferred embodiment of the claimed invention discloses a voltage-controlled delay line. The voltage-controlled delay line includes a clock generator for generating a first reference clock signal and a second reference clock signal, and a voltage-controlled delay line for delaying the first reference clock signal by a predetermined delay time to generate a first delay clock signal and delaying the second reference clock signal by the predetermined delay time to generate a second delay clock signal. The first reference clock signal and the first delay clock signal are in phase and the second reference clock signal and the second delay clock signal are in phase.
The voltage-controlled delay line includes a plurality of delay cells, and each delay cell has a first input port, a second input port, a first output port, and a second output port. The delay cells include a first delay cell, a second delay cell, a third delay cell, and a fourth delay cell. A first input port of the first delay cell is electrically connected to the clock generator for receiving the first reference clock signal. A first input port of the second delay cell is electrically connected to a first output port of the first delay cell through a first input port and a first output port of at least a fifth delay cell. A first output port of the second delay cell is electrically connected to a second input port of the first delay cell. A second input port of the second delay cell is electrically connected to a second output port of the first delay cell through a first input port and a first output port of at least a sixth delay cell and a second input port and a second output port of at least a fifth delay cell. A first input port of the third delay cell is electrically connected to the clock generator for receiving the second reference clock signal a second input port of the third delay cell electrically connected to a second output port of the second delay cell. A first input port of the fourth delay cell is electrically connected to a first output port of the third delay cell through a second output port and a second input port of at least a fifth delay cell and a first output port and a first input port of at least a sixth delay cell. A second input port of the fourth delay cell is electrically connected to a second output port of the third delay cell through a second input port and a second output port of at least a sixth delay cell. A first output port of the fourth delay cell is used for outputting the first delay clock signal. A second output port of the fourth delay cell is used for outputting the second delay clock signal. In addition, a total amount of the fifth delay cells is equal to a total amount of the sixth delay cells.
It is an advantage of the claimed invention that the claimed voltage-controlled delay line either connects a first output port of one delay cell and a second input port of another delay cell where the first output port of one delay cell and the second input port of another delay cell correspond to the same phase, or connects a first input port of one delay cell and a second output port of another delay cell where the first output port of one delay cell and the second input port of another delay cell correspond to the same phase. In other words, the first and second input ports of a delay cell are not simultaneously connected to the corresponding first and second output ports of an adjacent delay cell. Therefore, the timing errors associated with adjacent delay cells are independent so that the timing errors and the corresponding jitters are reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.